First exams 2027 · SL & HL 2027 年首次开考 · SL 与 HL

A1.2.5 · Computer fundamentals

A1.2.5 · 计算机基础

Construct Logic Diagrams

构建逻辑图

A1.2.4 read a circuit to get a table. This statement goes the other way: from a Boolean expression (or a problem description) to the wiring diagram, drawn with the standard gate symbols, and simplified first so it uses as few gates as possible.

A1.2.4 是读电路得到表格。本条考纲反过来:从布尔表达式(或问题描述)到接线图,用标准门符号画出来,并且先化简,让它用尽量少的门。

A1's guiding question asks what principles underpin how a computer works. Turning logic into a diagram of connected gates is the last step before that logic becomes real hardware.

A1 的引导性问题问的是支撑计算机运行的原理。把逻辑变成一张相连的门的图,是这段逻辑成为真实硬件之前的最后一步。

Core for SL & HL SL 与 HL 核心内容 Typically 2–5 marks · AO3 通常 2–5 分 · AO3 Command term: construct 命令词:construct(构建)

Explainer

讲解

Expression to circuit

从表达式到电路

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A logic diagram shows how gates are connected: inputs enter on the left, wires carry values between gates, and the single output leaves on the right. Each gate is drawn with its standard symbol (the seven from A1.2.3).

逻辑图展示门是如何连接的:输入从左边进入,导线在门之间传递值,唯一的输出从右边离开。每个门用它的标准符号画出(A1.2.3 里的那七种)。

The method: work from the inside of the expression outward. Draw the gates for the innermost brackets first, then the gates that combine their outputs, then the outermost gate. A NOT on a single variable is drawn right at that input.

方法:从表达式的最里层往外做。先画最里层括号对应的门,再画组合它们输出的门,最后画最外层的门。作用在单个变量上的 NOT,就画在那个输入的紧后面。

Order of operations 运算顺序

When an expression has no brackets, the order is NOT first, then AND (and NAND), then OR (and NOR and XOR). Brackets override this, exactly as they do in arithmetic.

当表达式没有括号时,顺序是先 NOT,然后 AND(和 NAND),最后 OR(和 NOR 和 XOR)。括号会改变这个顺序,和算术里完全一样。

Worked example

例题

Building a circuit gate by gate

一门一门地搭电路

Drawing the circuit for Y = (A AND B) OR (NOT A AND C). Step forward to add one gate at a time.

画 Y = (A AND B) OR (NOT A AND C) 的电路。逐步前进,每次加一个门。

Explainer

讲解

Boolean algebra rules

布尔代数规则

These identities let a long expression be rewritten as a shorter one that behaves identically. A shorter expression means fewer gates, so less cost, space, delay and power.

这些恒等式让一个长表达式被改写成一个行为完全相同、但更短的表达式。更短的表达式意味着更少的门,也就是更低的成本、更小的面积、更短的延迟和更少的功耗。

RuleAND formOR form
IdentityA · 1 = AA + 0 = A
Null (dominance)A · 0 = 0A + 1 = 1
IdempotentA · A = AA + A = A
ComplementA · A’ = 0A + A’ = 1
Double negation(A’)’ = A
CommutativeA · B = B · AA + B = B + A
DistributiveA · (B + C) = A·B + A·CA + (B·C) = (A+B) · (A+C)
AbsorptionA · (A + B) = AA + (A · B) = A
De Morgan(A · B)’ = A’ + B’(A + B)’ = A’ · B’
规则AND 形式OR 形式
同一律A · 1 = AA + 0 = A
零律(支配律)A · 0 = 0A + 1 = 1
幂等律A · A = AA + A = A
互补律A · A’ = 0A + A’ = 1
双重否定(A’)’ = A
交换律A · B = B · AA + B = B + A
分配律A · (B + C) = A·B + A·CA + (B·C) = (A+B) · (A+C)
吸收律A · (A + B) = AA + (A · B) = A
德摩根律(A · B)’ = A’ + B’(A + B)’ = A’ · B’

Worked example

例题

Simplify, then redraw

先化简,再重画

A design arrives as Y = A·B + A·B·C. Before drawing anything, simplify it.

一个设计给过来的形式是 Y = A·B + A·B·C。在画任何东西之前,先化简它。

StepWorkingRule
StartY = A·B + A·B·C–
1= A·B · (1 + C)Factor out A·B
2= A·B · 11 + C = 1 (null)
ResultY = A·BA·B · 1 = A·B (identity)
步骤推导规则
起始Y = A·B + A·B·C–
1= A·B · (1 + C)提取公因子 A·B
2= A·B · 11 + C = 1(零律)
结果Y = A·BA·B · 1 = A·B(同一律)

Before

化简前

Y = A·B + A·B·C

Needs: one 2-input AND, one 3-input AND, one OR gate.

需要:一个二输入 AND、一个三输入 AND、一个 OR 门。

After

化简后

Y = A·B

Needs: one 2-input AND gate. Input C is not used at all.

需要:一个二输入 AND 门。输入 C 根本用不到。

The two circuits give the same output for every input. If C makes no difference to A·B + A·B·C (and it does not), then wiring C in at all is wasted hardware.

这两个电路对每一种输入都给出相同的输出。如果 C 对 A·B + A·B·C 没有影响(确实没有),那么把 C 接进来就是浪费硬件。

Check your understanding

检验你的理解

What is the simplest logic diagram for Y = A + A·B?

Y = A + A·B 的最简逻辑图是什么?

Common mistake

常见错误

Recurring errors when drawing logic diagrams 画逻辑图时反复出现的错误

RecurringDrawing the circuit straight from the expression as given, without simplifying first, so it has more gates than it needs. A second slip: ignoring the order of operations, for example reading A + B · C as (A + B) · C. Without brackets, AND binds tighter than OR, so it is A + (B · C). A third: using the wrong symbol, most often drawing an OR (curved back) where an AND (flat back) is meant.

反复出现直接照着给定的表达式画电路,不先化简,结果门比需要的多。第二个错误:忽略运算顺序,例如把 A + B · C 读成 (A + B) · C。没有括号时,AND 比 OR 结合得更紧,所以是 A + (B · C)。第三个:用错符号,最常见的是在应该画 AND(平的背)的地方画了 OR(弯的背)。

✕

Wrong: "The expression is A·B + A·B·C, so I drew a 2-input AND, a 3-input AND and an OR to combine them, straight from the expression."

错误: "表达式是 A·B + A·B·C,所以我照着表达式画了一个二输入 AND、一个三输入 AND,再用一个 OR 把它们组合起来。"

✓

Right: "A·B + A·B·C simplifies to A·B (the C term is absorbed), so the diagram is a single 2-input AND gate with inputs A and B. Simplify the expression first, then draw the smaller circuit."

正确: "A·B + A·B·C 化简为 A·B(C 项被吸收),所以图就是一个二输入 AND 门,输入是 A 和 B。先化简表达式,再画更小的电路。"

Revision questions

复习题

Specimen-paper style. Write an answer, then reveal the marking points and mark yourself.

采用样卷风格。写下答案,然后展开评分要点给自己打分。

Question 1 · 2 marks 第 1 题 · 2 分

[2]Draw the logic diagram for Y = A AND (NOT B).

[2]画出 Y = A AND (NOT B) 的逻辑图。

Question 2 · 3 marks 第 2 题 · 3 分

[3]Draw the logic diagram for Y = (A OR B) AND (B OR C).

[3]画出 Y = (A OR B) AND (B OR C) 的逻辑图。

Question 3 · 4 marks 第 3 题 · 4 分

[4]Simplify Y = A·B·C + A·B·C’ using Boolean algebra, then draw the simplified logic diagram.

[4]用布尔代数化简 Y = A·B·C + A·B·C’,然后画出化简后的逻辑图。

Question 4 · 3 marks 第 4 题 · 3 分

[3]Use De Morgan's law to rewrite (A + B)’ without an OR gate, and draw the resulting circuit.

[3]用德摩根律把 (A + B)’ 改写成不含 OR 门的形式,并画出得到的电路。

Question 5 · 4 marks 第 5 题 · 4 分

[4]A lift door stays locked unless the lift is level with a floor and (the inside button or the outside button is pressed). Write the Boolean expression and draw the logic diagram.

[4]电梯门保持锁定,除非电梯与某一层齐平、并且(内部按钮或外部按钮被按下)。写出布尔表达式并画出逻辑图。

Flashcards

记忆卡片

Active recall for this statement’s key terms.

针对本条考纲陈述关键术语的主动回忆练习。

Prototype render · grounded in the IB CS 2027 subject guide and the Hodder and Oxford IB CS 2027 texts for A1.2.5 · not yet wired to live routes