A1.1.4 · Computer fundamentals
A1.1.4 · 计算机基础
Types of Primary Memory
主存储器的类型
The CPU does not wait the same amount of time for every piece of data. Right beside it sits memory it can reach in a fraction of a nanosecond; a little further out, memory that takes about fifty times longer. The four types of primary memory are built around that gap.
CPU 并不是对每一个数据都等待相同的时间。紧挨着它的是它能在几分之一纳秒内取到的内存;稍远一点,是要慢大约五十倍的内存。四种主存储器就是围绕这个差距而设计的。
A1's guiding question asks what principles underpin how a computer works. Here the principle is a memory hierarchy: keep the data you need most often in the fastest, smallest store, and accept a delay for the rest.
A1 的引导性问题问的是支撑计算机运行的原理。这里的原理是内存层级:把最常用的数据放在最快、最小的存储区,其余的则接受一定的延迟。
Explainer
讲解
The four types
四种类型
Primary memory is the memory the CPU can use directly, without going through secondary storage first. It holds the data and instructions currently in use. The four types are registers, cache, RAM and ROM.
主存储器是 CPU 能直接使用、不必先经过二级存储器的内存。它保存当前正在使用的数据和指令。四种类型是寄存器、缓存、RAM 和 ROM。
| Type | What it holds | Speed & size | Purpose |
|---|---|---|---|
| Registers | The operands, addresses and results the CPU is using right this instant (see A1.1.1) | Fastest, smallest; inside the CPU; volatile | Give the ALU and control unit somewhere to keep the current values with no delay at all |
| Cache (L1, L2, L3) | Copies of the data and instructions the CPU has used recently or often | Very fast, small; on or next to the CPU; L1 smallest and fastest per core, L3 largest and slowest, often shared; volatile | Bridge the large speed gap between registers and RAM, so the CPU rarely has to wait for RAM |
| RAM | The running operating system, open programs, and their active data | Slower than cache, much larger (gigabytes); volatile | The main working area; anything the CPU runs is loaded here first |
| ROM | Fixed start-up instructions (the BIOS or firmware) that rarely change | Small; non-volatile (keeps its contents with no power) | Holds the code that runs when the machine is switched on: test the hardware, then load the operating system from storage into RAM |
| 类型 | 它保存什么 | 速度与容量 | 用途 |
|---|---|---|---|
| 寄存器 | CPU 此刻正在使用的操作数、地址和结果(见 A1.1.1) | 最快、最小;在 CPU 内部;易失 | 给 ALU 和控制单元一个地方,能毫无延迟地保存当前的值 |
| 缓存(L1、L2、L3) | CPU 最近或经常用到的数据和指令的副本 | 非常快、容量小;在 CPU 上或紧邻 CPU;L1 每核最小最快,L3 最大最慢且常被共享;易失 | 弥合寄存器与 RAM 之间巨大的速度差距,使 CPU 很少需要等待 RAM |
| RAM | 正在运行的操作系统、打开的程序及其活动数据 | 比缓存慢,容量大得多(以 GB 计);易失 | 主工作区;CPU 运行的任何东西都先被加载到这里 |
| ROM | 很少改变的固定开机指令(BIOS 或固件) | 容量小;非易失(断电也保留内容) | 保存机器开机时运行的代码:测试硬件,然后把操作系统从存储器加载到 RAM |
Registers, cache and RAM are all volatile: switch the power off and their contents are gone. ROM is non-volatile: it keeps its contents, which is exactly why the start-up code lives there, it has to survive being switched off.
寄存器、缓存和 RAM 都是易失的:一断电,里面的内容就没了。ROM 是非易失的:它会保留内容,这正是开机代码放在那里的原因,它必须在断电后依然存在。
Explainer
讲解
The hierarchy, and why it exists
层级结构及其存在的原因
Registers, L1, L2, L3 and RAM form a ladder. Each rung down is larger but slower. When the CPU needs a value it checks them in order from the top: registers, then L1, then L2, then L3, then RAM. It stops at the first one that has the value.
寄存器、L1、L2、L3 和 RAM 构成一个阶梯。每往下一级,容量更大但速度更慢。当 CPU 需要某个值时,它从最上面开始按顺序检查:寄存器,然后 L1、L2、L3,然后 RAM。一旦某一级有这个值,它就停下。
The point of the ladder is to make the fast levels do most of the work. Because programs tend to reuse the same data and nearby data (this is called locality), a small cache close to the CPU catches most requests, and the slow trip to RAM is rare. Modern CPUs also prefetch: they predict what data will be needed next and load it into cache early.
这个阶梯的意义在于让快的层级承担大部分工作。由于程序往往会重复使用相同的数据以及邻近的数据(这叫做局部性),一个紧邻 CPU 的小缓存就能接住大多数请求,而去 RAM 的慢速往返很少发生。现代 CPU 还会预取:预测接下来会用到什么数据,提前加载到缓存里。
Explainer
讲解
Cache hit and cache miss
缓存命中与缓存未命中
A cache hit is when the CPU asks for data and finds it in the cache, this is the fast case. A cache miss is when it is not in the cache, so the CPU has to fetch it from the slower RAM (or slower still, from storage), causing a delay.
缓存命中是指 CPU 请求数据时在缓存里找到了它,这是快的情况。缓存未命中是指数据不在缓存里,于是 CPU 必须从较慢的 RAM(或更慢的存储器)去取,造成延迟。
The fraction of requests that are hits is the hit rate. A higher hit rate means the CPU spends less time waiting, so the whole system runs faster. A larger cache and better prefetching both raise the hit rate.
请求中命中的比例叫做命中率。命中率越高,CPU 花在等待上的时间越少,整个系统就跑得越快。更大的缓存和更好的预取都能提高命中率。
Step through
逐步演示
Where does the CPU find the data?
CPU 在哪里找到数据?
The CPU needs one value. Step through the hierarchy and watch the delay grow at each level it misses. In this run the value is found in L2.
CPU 需要一个值。逐步走过这个层级,看看每错过一级、延迟就增长一点。在这次演示里,值在 L2 中被找到。
Check your understanding
检验你的理解
What happens on a cache miss?
缓存未命中时会发生什么?
Common mistake
常见错误
RecurringWeak answers treat cache as "a small piece of RAM" or ROM as "slow RAM". Cache is a separate, faster memory that sits between the CPU and RAM and holds copies of frequently used data. ROM is not part of the register, cache, RAM hierarchy at all: it is non-volatile and its only job is to hold the start-up code. Another slip is calling RAM non-volatile: it forgets everything the moment power is removed, which is why unsaved work disappears.
反复出现薄弱的答案把缓存说成"一小块 RAM",或把 ROM 说成"慢速 RAM"。缓存是一种独立的、更快的内存,位于 CPU 与 RAM 之间,保存常用数据的副本。ROM 根本不属于"寄存器、缓存、RAM"这个层级:它是非易失的,唯一的工作就是保存开机代码。另一个错误是把 RAM 说成非易失的,它一断电就丢失内容,这正是未保存的工作会丢失的原因。
Blurs the types: "Cache is a bit of the RAM set aside for the CPU, and ROM is just permanent RAM."
把类型混为一谈: "缓存是 RAM 里划给 CPU 的一小块,ROM 就是永久的 RAM。"
Keeps them distinct: "Cache is separate, faster memory between the CPU and RAM, holding copies of recently used data to cut the wait for RAM. ROM is non-volatile memory holding the fixed start-up code; it is not part of the day-to-day register, cache, RAM path."
让它们各自分明: "缓存是位于 CPU 与 RAM 之间的一种独立、更快的内存,保存最近用过的数据的副本,以减少对 RAM 的等待。ROM 是保存固定开机代码的非易失内存;它不属于日常的'寄存器、缓存、RAM'这条路径。"
Revision questions
复习题
Specimen-paper style. Write an answer, then reveal the marking points and mark yourself.
采用样卷风格。写下答案,然后展开评分要点给自己打分。
[2]Explain what a cache hit is, and what a cache miss is.
[2]解释什么是缓存命中,什么是缓存未命中。
Marking points
评分要点
- A cache hit is when the CPU asks for data and finds it in the cache (the fast case).
- A cache miss is when the data is not in the cache, so the CPU has to fetch it from the slower RAM (or from storage), causing a delay.
- 缓存命中是指 CPU 请求数据并在缓存中找到它(快的情况)。
- 缓存未命中是指数据不在缓存中,所以 CPU 必须从较慢的 RAM(或存储器)取回它,造成延迟。
[3]Explain one purpose of ROM and one reason it must be non-volatile.
[3]解释 ROM 的一项用途,以及它必须是非易失的一个原因。
Marking points
评分要点
- One purpose: ROM holds the fixed start-up instructions (the BIOS or firmware) that run when the machine is switched on, to test the hardware and load the operating system into RAM.
- It must be non-volatile because RAM is empty at power-on, so if the start-up code were volatile there would be no instructions to start the machine at all.
- 一个用途:ROM 存放开机时运行的固定启动指令(BIOS 或固件),用来检测硬件并把操作系统载入 RAM。
- 它必须是非易失的,因为开机时 RAM 是空的,所以如果启动代码是易失的,就根本没有指令来启动机器。
[4]Explain how the levels of cache (L1, L2, L3) differ, and why more than one level is used.
[4]解释各级缓存(L1、L2、L3)有何不同,以及为什么要使用不止一级。
Marking points
评分要点
- L1 is the smallest and fastest, on each core; L2 is larger and a little slower; L3 is the largest and slowest, often shared between cores.
- More than one level is used so the speed gap between the registers and RAM is bridged in stages: a tiny very-fast level catches the most-used data, and each larger level catches what the level above missed, so the CPU rarely waits for RAM.
- L1 最小、最快,在每个核心上;L2 更大、稍慢;L3 最大、最慢,常在核心之间共享。
- 使用多个层级,是为了分阶段地弥合寄存器与 RAM 之间的速度差距:一个极小的极快层级接住最常用的数据,每个更大的层级接住上一层未命中的数据,这样 CPU 很少需要等待 RAM。
[4]Explain how registers, cache and RAM form a hierarchy that keeps the CPU from having to wait on RAM as often.
[4]解释寄存器、缓存和 RAM 如何构成一个层级,从而减少 CPU 等待数据的时间。
Marking points
评分要点
- Registers, L1, L2, L3 and RAM form a ladder: each level down is larger but slower.
- When the CPU needs a value it checks from the top and stops at the first level that holds it.
- Because programs reuse the same and nearby data (locality), the small fast levels near the CPU satisfy most requests, so the slow trip to RAM is only needed occasionally.
- 寄存器、L1、L2、L3 和 RAM 构成一个阶梯:往下每一级更大但更慢。
- CPU 需要某个值时,从顶端开始检查,在第一个含有它的级别停下。
- 由于程序重复使用相同和邻近的数据(局部性),CPU 附近那些又小又快的级别满足了大多数请求,所以只有偶尔才需要去 RAM 那趟慢路。
[2]State why work in an open program is lost if the power fails before it is saved.
[2]说明为什么在保存之前断电,打开的程序中的工作会丢失。
Marking points
评分要点
- RAM is volatile: it only holds its contents while it is powered.
- If the power fails, the RAM contents (including the unsaved work in the open program) are lost, because a saved copy has not yet been written to non-volatile secondary storage.
- RAM 是易失的:只有在通电时才保留内容。
- 如果断电,RAM 的内容(包括打开的程序中未保存的工作)就会丢失,因为还没有把保存的副本写入非易失的二级存储。
Flashcards
记忆卡片
Active recall for this statement’s key terms.
针对本条考纲陈述关键术语的主动回忆练习。
Keep this statement’s practice with you
把这条考纲陈述的练习保存下来
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免费账户:解锁 A1.1.4 以及所有其他 IB CS 2027 考纲陈述的全部复习题和记忆卡片。