First exams 2027 · SL & HL 2027 年首次开考 · SL 与 HL

A1.1.5 · Computer fundamentals

A1.1.5 · 计算机基础

The Fetch, Decode and Execute Cycle

取指、译码、执行周期

A processor does not run a program in one leap. It repeats one tiny three-step loop, fetch, decode, execute, once for every single machine-code instruction, billions of times a second.

处理器不是一跃而过地运行一个程序。它重复一个很小的三步循环(取指、译码、执行),对每一条机器码指令各执行一次,每秒重复数十亿次。

A1's guiding question asks what principles underpin how a computer works. This is the most basic one: every program, however large, is this loop run over and over. It ties together the components from A1.1.1.

A1 的引导性问题问的是支撑计算机运行的原理。这是最基础的一个:任何程序,无论多大,都是这个循环一遍遍地运行。它把 A1.1.1 里的各个部件串联在一起。

Core for SL & HL SL 与 HL 核心内容 Typically 3–6 marks · AO2 通常 3–6 分 · AO2 Command term: describe 命令词:describe(描述)

Explainer

讲解

One three-step loop

一个三步循环

Df

The fetch, decode and execute cycle (also called the instruction cycle) is the process the CPU repeats for every machine-code instruction: fetch the instruction from memory, decode what it means, then execute it. Then it starts again on the next instruction.

取指、译码、执行周期(也叫指令周期)是 CPU 对每一条机器码指令都重复的过程:从内存取指、译码出它的含义、然后执行它。之后再对下一条指令重新开始。

How fast the CPU can run this loop is what "processing speed" mostly comes down to. A 3 GHz clock means the CPU steps through this cycle about three billion times per second.

CPU 能多快地运行这个循环,基本上就是"处理速度"所指的东西。3 GHz 的时钟意味着 CPU 每秒大约走过这个周期三十亿次。

Explainer

讲解

Each stage, with the registers and buses

各阶段与相关的寄存器和总线

A strong answer names the registers (PC, MAR, MDR, IR, AC) and the buses (address, data, control) covered in A1.1.1. Three boxes labelled "fetch, decode, execute" is not a description.

好的答案会点出 A1.1.1 里的寄存器(PC、MAR、MDR、IR、AC)和总线(地址、数据、控制)。画三个写着"取指、译码、执行"的方框不算描述。

StageWhat happens
FetchThe address in the PC is placed in the MAR. That address goes to memory on the address bus; a read signal goes on the control bus. The instruction comes back on the data bus into the MDR, and is copied into the IR. The PC is increased so it points at the next instruction.
DecodeThe control unit takes the instruction now held in the IR and works out the opcode (which operation) and the operand (the data or the address to act on).
ExecuteThe control unit sends control signals on the control bus and the operation is carried out. For a calculation the ALU acts, using the accumulator. For a load or store, memory is accessed again over the buses.
阶段发生的过程
取指PC 中的地址被放入 MAR。该地址沿地址总线送到内存;一个读信号沿控制总线发出。指令沿数据总线返回到 MDR,并被复制到 IR 中。PC 增加,使其指向下一条指令。
译码控制单元取出此刻位于 IR 中的那条指令,判断出操作码(要做哪种操作)和操作数(要作用的数据或地址)。
执行控制单元沿控制总线发出控制信号,操作被执行。若是运算,则由 ALU 借助累加器完成。若是加载或存储,则再次通过总线访问内存。

Step through

逐步演示

One ADD instruction

一条 ADD 指令

One instruction, ADD 6 ("add the number at address 6 to the accumulator"), stored at address 3. Step forward and watch the value move between registers as the buses light up.

一条指令 ADD 6("把地址 6 处的数加到累加器上"),存储在地址 3。逐步前进,观察数值在寄存器之间移动、总线随之点亮。

Check your understanding

检验你的理解

What happens during the decode stage of the cycle?

周期的译码阶段发生了什么?

Common mistake

常见错误

Recurring weaknesses when this cycle is described 描述这个周期时反复出现的弱点

RecurringAsked about decode, many answers describe execute instead ("the ALU does the calculation"). Decode is only the control unit reading the instruction in the IR and working out the operation. Two more slips: putting the PC increment in the execute stage (it happens during fetch), and answering with three unlabelled boxes rather than naming the registers and buses involved.

反复出现被问到译码时,许多答案却描述了执行("ALU 做运算")。译码只是控制单元读取 IR 中的指令并判断出操作。还有两个错误:把 PC 加 1 放进执行阶段(它发生在取指阶段),以及用三个没有标注的方框来作答,而不点出涉及的寄存器和总线。

✕

Decode as execute: "In the decode stage the CPU carries out the instruction and the ALU adds the numbers."

把译码当成执行: "在译码阶段,CPU 执行这条指令,ALU 把数字相加。"

✓

Right: "In decode, the control unit takes the instruction now in the IR and works out the opcode and operand. The instruction is only carried out afterwards, in the execute stage."

正确: "在译码阶段,控制单元读取此刻位于 IR 中的指令,判断出操作码和操作数。这条指令要到之后的执行阶段才被真正执行。"

Revision questions

复习题

Specimen-paper style. Write an answer, then reveal the marking points and mark yourself.

采用样卷风格。写下答案,然后展开评分要点给自己打分。

Question 1 · 3 marks 第 1 题 · 3 分

[3]Describe the fetch stage of the cycle, naming the registers and buses used.

[3]描述周期的取指阶段,点出所使用的寄存器和总线。

Question 2 · 2 marks 第 2 题 · 2 分

[2]Describe what the control unit does during the decode stage.

[2]描述译码阶段控制单元做什么。

Question 3 · 6 marks 第 3 题 · 6 分

[6]Trace one ADD instruction through the fetch stage, then decode, then execute, from the program counter to the result in the accumulator.

[6]追踪一条 ADD 指令依次经过取指、译码、执行,从程序计数器一直到结果存入累加器。

Question 4 · 2 marks 第 4 题 · 2 分

[2]State at which stage the program counter is incremented, and why it is done then.

[2]说明程序计数器在哪个阶段加 1,以及为什么在那时进行。

Question 5 · 3 marks 第 5 题 · 3 分

[3]Explain how the three buses (address, data, control) are each used during one pass through the cycle.

[3]解释在一次完整的周期中,三条总线(地址、数据、控制)各自如何被使用。

Flashcards

记忆卡片

Active recall for this statement’s key terms.

针对本条考纲陈述关键术语的主动回忆练习。

Prototype render · grounded in the IB CS 2027 subject guide, the Hodder and Oxford IB CS 2027 texts, and the specimen papers for A1.1.5 · not yet wired to live routes