A1.1.6 · Computer fundamentals · HL
A1.1.6 · 计算机基础 · HL
Pipelining in Multi-Core Architectures
多核架构中的流水线
In A1.1.5 the CPU finished one instruction completely before starting the next, which left most of the processor idle at any moment. Pipelining fixes that: as one instruction runs through execute, the next is already in decode, and a third is being fetched.
在 A1.1.5 中,CPU 要把一条指令完全做完才开始下一条,这让处理器在任何时刻大部分都闲着。流水线解决了这个问题:当一条指令正在执行时,下一条已经在译码,再下一条已经在取指。
A1's guiding question asks what principles underpin how a computer works. Pipelining is one: get more done with the same hardware by never letting a stage sit idle.
A1 的引导性问题问的是支撑计算机运行的原理。流水线就是其中之一:用同样的硬件做更多的事,办法是绝不让任何一个阶段闲着。
Explainer
讲解
The idea: overlap the stages
核心思路:让各阶段重叠
Pipelining is a technique that overlaps the execution of several instructions by splitting the instruction cycle into separate stages and letting each stage work on a different instruction at the same time.
流水线是一种技术:它把指令周期拆成若干独立的阶段,让每个阶段同时处理不同的指令,从而使多条指令的执行相互重叠。
Think of a passport queue with four booths: scan the passport, check the photo against the face, ask a question, stamp. Without pipelining, one traveller goes through all four booths before the next traveller starts, so three booths are always empty. With pipelining, as soon as traveller A leaves the scan booth, traveller B steps into it. After a short warm-up, all four booths are busy at once, and one traveller comes out at the end of every step.
想象一个有四个窗口的过关队伍:扫描护照、核对照片与人脸、问一个问题、盖章。没有流水线时,一位旅客要走完全部四个窗口,下一位才开始,所以总有三个窗口空着。有了流水线,旅客 A 一离开扫描窗口,旅客 B 就走进去。经过短暂的启动之后,四个窗口同时都在忙,而且每走一步就有一位旅客从末端出来。
The processor is the same. Its speed is limited by the hardware and making it faster is expensive; getting more use out of what is already there is cheaper. A well-filled pipeline can finish close to one instruction every clock cycle.
处理器也是一样。它的速度受硬件限制,提升硬件很贵;把已有的东西用得更充分则便宜得多。一条填满的流水线可以接近每个时钟周期完成一条指令。
Explainer
讲解
The stages, including write-back
各阶段,包括写回
A common pipeline splits the instruction cycle into five stages. The first three are the fetch, decode and execute from A1.1.5; a full pipeline adds two more.
常见的流水线把指令周期拆成五个阶段。前三个就是 A1.1.5 里的取指、译码、执行;完整的流水线还要再加两个。
| Stage | What it does |
|---|---|
| Fetch | Get the next instruction from memory |
| Decode | Work out the operation and the operands |
| Execute | Carry out the operation (for a calculation, in the ALU) |
| Memory access | Read or write any data the instruction needs from or to memory |
| Write-back | Write the result of the instruction back into a CPU register |
| 阶段 | 它做什么 |
|---|---|
| 取指 | 从内存取出下一条指令 |
| 译码 | 判断出操作和操作数 |
| 执行 | 执行操作(若是运算,则在 ALU 中进行) |
| 内存访问 | 为这条指令从内存读取或向内存写入所需的数据 |
| 写回 | 把这条指令的结果写回 CPU 的一个寄存器 |
Small registers between the stages hold each instruction's partly-finished result and pass it on. A single clock signal steps every stage forward together, so on each tick every instruction in the pipeline moves one stage along.
阶段之间有一些小寄存器,保存每条指令做到一半的结果,并把它传给下一阶段。一个统一的时钟信号让每个阶段一起向前推进,所以每一拍,流水线里的每条指令都往前挪一个阶段。
Step through
逐步演示
Filling the pipeline
填满流水线
Four instructions, five stages. Step through the clock cycles and watch the diagonal fill: from cycle 5 onward, all five stages are busy, and one instruction finishes every cycle.
四条指令,五个阶段。逐个时钟周期地推进,看着这条对角线被填满:从第 5 个周期起,五个阶段全都在忙,而且每个周期都有一条指令完成。
Without pipelining these four instructions would take 4 × 5 = 20 cycles. Pipelined, they take 8: five to fill the pipeline for the first instruction, then one more per instruction after it.
没有流水线时,这四条指令要花 4 × 5 = 20 个周期。用流水线,只要 8 个:头 5 个周期把流水线为第一条指令填满,之后每条指令再加 1 个周期。
Explainer
讲解
One pipeline per core
每个核心一条流水线
A multi-core processor has several cores, and each core has its own pipeline. Two things follow.
多核处理器有多个核心,而每个核心都有自己的流水线。由此有两点。
Independent execution: each core runs its own stream of instructions through its own pipeline. If one core is busy with a heavy task, the others carry on with their own work without waiting for it.
独立执行:每个核心通过自己的流水线运行自己的一串指令。如果一个核心正忙于繁重的任务,其他核心就继续做各自的工作,不必等它。
Parallel execution: when one large task can be split into parts (for example, the threads of a multi-threaded program), the parts can be given to different cores and run at the same time, each in its own pipeline. This finishes the whole task sooner.
并行执行:当一个大任务能被拆成多个部分时(例如一个多线程程序的各个线程),这些部分可以交给不同的核心,同时运行,各自在自己的流水线里。这样整个任务能更快完成。
So a multi-core CPU gets speed from two directions at once: pipelining keeps every stage of one core busy, and multiple cores keep several instruction streams moving in parallel.
所以多核 CPU 同时从两个方向获得速度:流水线让一个核心的每个阶段都保持忙碌,而多个核心让若干条指令流并行推进。
Check your understanding
检验你的理解
How does pipelining improve performance?
流水线是如何提升性能的?
Common mistake
常见错误
RecurringA weak answer says pipelining "speeds up each instruction". It does not: an instruction still passes through every stage and takes the same number of cycles from start to finish. Pipelining raises throughput, the number of instructions completed per second, by overlapping them. A second slip is confusing pipelining with parallel execution: pipelining overlaps the stages of instructions within one core; parallel execution runs whole instruction streams on different cores at once. A multi-core CPU uses both.
反复出现薄弱的答案说流水线"让每条指令更快"。并非如此:一条指令仍然要经过每一个阶段,从头到尾花的周期数不变。流水线通过让指令相互重叠,提高的是吞吐量,即每秒完成的指令数量。第二个错误是把流水线和并行执行混为一谈:流水线让一个核心内多条指令的各阶段相互重叠;并行执行是让完整的指令流同时在不同的核心上运行。多核 CPU 两者都用。
Wrong target: "Pipelining makes the fetch, decode and execute of one instruction happen faster."
搞错了对象: "流水线让一条指令的取指、译码、执行发生得更快。"
Right: "Each instruction still takes the same number of cycles, but because a new instruction enters the pipeline every cycle, once the pipeline is full one instruction finishes each cycle instead of every five, so the CPU completes far more instructions per second."
正确: "每条指令花的周期数仍然一样,但由于每个周期都有一条新指令进入流水线,一旦流水线填满,就变成每个周期完成一条指令,而不是每五个周期一条,所以 CPU 每秒完成的指令多得多。"
Revision questions
复习题
Specimen-paper style. Write an answer, then reveal the marking points and mark yourself.
采用样卷风格。写下答案,然后展开评分要点给自己打分。
[3]Describe what pipelining is and how it improves performance.
[3]描述什么是流水线,以及它如何提升性能。
Marking points
评分要点
- Pipelining splits the instruction cycle into separate stages (fetch, decode, execute, memory access, write-back).
- Each stage works on a different instruction at the same time, so the stages overlap instead of one instruction finishing before the next starts.
- Once the pipeline is full, one instruction completes every clock cycle, so throughput (instructions finished per second) is much higher.
- 流水线把指令周期拆成若干独立阶段(取指、译码、执行、内存访问、写回)。
- 每个阶段同时处理不同的指令,所以各阶段相互重叠,而不是一条指令做完才开始下一条。
- 一旦流水线填满,每个时钟周期完成一条指令,所以吞吐量(每秒完成的指令数)大得多。
[2]Name the five stages of a common instruction pipeline, in order.
[2]按顺序说出常见指令流水线的五个阶段。
[4]Compare how a non-pipelined CPU and a pipelined CPU execute a sequence of four instructions.
[4]比较一个非流水线 CPU 和一个流水线 CPU 如何执行由四条指令组成的序列。
Marking points
评分要点
- Non-pipelined: instruction 1 goes through all five stages before instruction 2 begins, so four instructions take about 4 x 5 = 20 cycles.
- Pipelined: instruction 2 enters fetch as soon as instruction 1 moves to decode, so the stages overlap.
- After the pipeline fills (five cycles for the first instruction), one instruction finishes every cycle, so four instructions take about 8 cycles.
- 非流水线:指令 1 走完全部五个阶段,指令 2 才开始,所以四条指令约需 4 x 5 = 20 个周期。
- 流水线:指令 1 一进入译码,指令 2 就进入取指,所以各阶段重叠。
- 流水线填满后(第一条指令用五个周期),之后每个周期完成一条指令,所以四条指令约需 8 个周期。
[4]Explain how a multi-core processor uses pipelining and parallel execution together to improve performance.
[4]解释多核处理器如何同时使用流水线和并行执行来提升性能。
Marking points
评分要点
- Pipelining keeps every stage of one core busy: a new instruction enters that core's pipeline each cycle, so the core finishes close to one instruction per cycle.
- Multiple cores add parallel execution: a task split into parts (for example threads) is run on different cores at the same time, each core using its own pipeline.
- So a multi-core CPU gains speed from two directions at once.
- 流水线让一个核心的每个阶段都保持忙碌:每个周期都有一条新指令进入该核心的流水线,所以这个核心接近每周期完成一条指令。
- 多个核心加上并行执行:一个被拆成多个部分(例如线程)的任务在不同核心上同时运行,每个核心使用自己的流水线。
- 所以多核 CPU 同时从两个方向获得速度。
[2]Distinguish between the independent execution and the parallel execution of cores in a multi-core processor.
[2]区分多核处理器中各核心的独立执行与并行执行。
Marking points
评分要点
- Independent execution: each core runs its own separate stream of instructions; if one core is busy the others carry on with their own work.
- Parallel execution: one task is split into parts and those parts are run on different cores at the same time to finish the whole task sooner.
- 独立执行:每个核心运行自己独立的一串指令;如果一个核心在忙,其他核心继续做各自的工作。
- 并行执行:一个任务被拆成多个部分,这些部分在不同核心上同时运行,以便更快完成整个任务。
Flashcards
记忆卡片
Active recall for this statement’s key terms.
针对本条考纲陈述关键术语的主动回忆练习。
Keep this statement’s practice with you
把这条考纲陈述的练习保存下来
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免费账户:解锁 A1.1.6 以及所有其他 IB CS 2027 考纲陈述的全部复习题和记忆卡片。